Shivani Raghav, Martino Ruggiero, David Atienza, Christian Pinto, Andrea Marongiu, Luca Benini. Scalable instruction set simulator for thousand-core architectures running on GPGPUs. In Waleed W. Smari, John P. McIntire, editors, Proceedings of the 2010 International Conference on High Performance Computing & Simulation, HPCS 2010, June 28 - July 2, 2010, Caen, France. pages 459-466, IEEE, 2010. [doi]
@inproceedings{RaghavRAPMB10,
title = {Scalable instruction set simulator for thousand-core architectures running on GPGPUs},
author = {Shivani Raghav and Martino Ruggiero and David Atienza and Christian Pinto and Andrea Marongiu and Luca Benini},
year = {2010},
doi = {10.1109/HPCS.2010.5547092},
url = {http://dx.doi.org/10.1109/HPCS.2010.5547092},
tags = {architecture},
researchr = {https://researchr.org/publication/RaghavRAPMB10},
cites = {0},
citedby = {0},
pages = {459-466},
booktitle = {Proceedings of the 2010 International Conference on High Performance Computing & Simulation, HPCS 2010, June 28 - July 2, 2010, Caen, France},
editor = {Waleed W. Smari and John P. McIntire},
publisher = {IEEE},
isbn = {978-1-4244-6828-7},
}