Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas. Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. In 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA. pages 43-46, IEEE Computer Society, 2008. [doi]
Abstract is missing.