Mohammed Ziaur Rahman. A Combined Arithmetic Logic Unit and Memory Element for the Design of a Parallel Computer. In Yang Xiang, Alfredo Cuzzocrea, Michael Hobbs, Wanlei Zhou, editors, Algorithms and Architectures for Parallel Processing - 11th International Conference, ICA3PP, Melbourne, Australia, October 24-26, 2011, Proceedings, Part I. Volume 7016 of Lecture Notes in Computer Science, pages 306-317, Springer, 2011. [doi]
@inproceedings{Rahman11-1,
title = {A Combined Arithmetic Logic Unit and Memory Element for the Design of a Parallel Computer},
author = {Mohammed Ziaur Rahman},
year = {2011},
doi = {10.1007/978-3-642-24650-0_26},
url = {http://dx.doi.org/10.1007/978-3-642-24650-0_26},
researchr = {https://researchr.org/publication/Rahman11-1},
cites = {0},
citedby = {0},
pages = {306-317},
booktitle = {Algorithms and Architectures for Parallel Processing - 11th International Conference, ICA3PP, Melbourne, Australia, October 24-26, 2011, Proceedings, Part I},
editor = {Yang Xiang and Alfredo Cuzzocrea and Michael Hobbs and Wanlei Zhou},
volume = {7016},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-642-24649-4},
}