Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator - researchr publication authors

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Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi. Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. In Luigi Dilillo, Mihalis Psarakis, Taniya Siddiqua, editors, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, Frascati, Italy, October 19-21, 2020. pages 1-4, IEEE, 2020. [doi]

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