George P. Rajesh, C. K. Deepthy, M. Mary Jermila, K. P. Raghunath, Vishnu N. Aparna. Force Rebalance with Multi-bit Sigma-Delta implemented with FPGA for Precision Rate Sensor. In TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), Kochi, India, October 17-20, 2019. pages 654-657, IEEE, 2019. [doi]
@inproceedings{RajeshDJRA19,
title = {Force Rebalance with Multi-bit Sigma-Delta implemented with FPGA for Precision Rate Sensor},
author = {George P. Rajesh and C. K. Deepthy and M. Mary Jermila and K. P. Raghunath and Vishnu N. Aparna},
year = {2019},
doi = {10.1109/TENCON.2019.8929279},
url = {https://doi.org/10.1109/TENCON.2019.8929279},
researchr = {https://researchr.org/publication/RajeshDJRA19},
cites = {0},
citedby = {0},
pages = {654-657},
booktitle = {TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), Kochi, India, October 17-20, 2019},
publisher = {IEEE},
isbn = {978-1-7281-1895-6},
}