N. Rajput, M. Sethi, P. Dobriyal, K. Sharma, G. Sharma. A novel, high performance and power efficient implementation of 8×8 multiplier unit using MT-CMOS technique. In Manish Parashar, Albert Y. Zomaya, Jianer Chen, Jiannong Cao, Pascal Bouvry, Sushil K. Prasad, editors, Sixth International Conference on Contemporary Computing, IC3 2013, Noida, India, August 8-10, 2013. pages 186-191, IEEE, 2013. [doi]
@inproceedings{RajputSDSS13,
title = {A novel, high performance and power efficient implementation of 8×8 multiplier unit using MT-CMOS technique},
author = {N. Rajput and M. Sethi and P. Dobriyal and K. Sharma and G. Sharma},
year = {2013},
doi = {10.1109/IC3.2013.6612187},
url = {http://dx.doi.org/10.1109/IC3.2013.6612187},
researchr = {https://researchr.org/publication/RajputSDSS13},
cites = {0},
citedby = {0},
pages = {186-191},
booktitle = {Sixth International Conference on Contemporary Computing, IC3 2013, Noida, India, August 8-10, 2013},
editor = {Manish Parashar and Albert Y. Zomaya and Jianer Chen and Jiannong Cao and Pascal Bouvry and Sushil K. Prasad},
publisher = {IEEE},
}