N. Rajput, M. Sethi, P. Dobriyal, K. Sharma, G. Sharma. A novel, high performance and power efficient implementation of 8×8 multiplier unit using MT-CMOS technique. In Manish Parashar, Albert Y. Zomaya, Jianer Chen, Jiannong Cao, Pascal Bouvry, Sushil K. Prasad, editors, Sixth International Conference on Contemporary Computing, IC3 2013, Noida, India, August 8-10, 2013. pages 186-191, IEEE, 2013. [doi]
Abstract is missing.