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A Power and Performance Simulator for a Single-Chip Message-Passing Parallel Architecture

Priyadarshini Ramachandran, Charles W. Lewis Jr., James M. Baker Jr.. A Power and Performance Simulator for a Single-Chip Message-Passing Parallel Architecture. In Hamid R. Arabnia, Rose Joshua, Iyad A. Ajwa, George A. Gravvanis, editors, Proceedings of the International Conference on Modeling, Simulation & Visualization Methods, MSV 04 & Proceedings of the International Conference on Algorithmic Mathematics & Computer Science, AMCS 04, June 21-24, 2004, Las Vegas, Nevada, US. pages 31-37, CSREA Press, 2004.

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