Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

Srilata Raman, C. L. Liu 0001, Larry G. Jones. Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. VLSI Design, 4(4):345-355, 1996. [doi]

Authors

Srilata Raman

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C. L. Liu 0001

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Larry G. Jones

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