Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations

Parameswaran Ramanathan, Kewal K. Saluja. Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016. pages 7-12, IEEE Computer Society, 2016. [doi]

Abstract

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