Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator - researchr publication authors

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Krishna Sai Tarun Ramapragada, Ajith Kumar Reddy Netla, Pavan Kalyan Chattada, Bhaskar Manickam. Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator. In IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021. pages 93-98, IEEE, 2021. [doi]

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