Krishna Sai Tarun Ramapragada, Ajith Kumar Reddy Netla, Pavan Kalyan Chattada, Bhaskar Manickam. Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator. In IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021. pages 93-98, IEEE, 2021. [doi]
@inproceedings{RamapragadaNCM21,
title = {Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator},
author = {Krishna Sai Tarun Ramapragada and Ajith Kumar Reddy Netla and Pavan Kalyan Chattada and Bhaskar Manickam},
year = {2021},
doi = {10.1109/iSES52644.2021.00032},
url = {https://doi.org/10.1109/iSES52644.2021.00032},
researchr = {https://researchr.org/publication/RamapragadaNCM21},
cites = {0},
citedby = {0},
pages = {93-98},
booktitle = {IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021},
publisher = {IEEE},
isbn = {978-1-7281-8753-2},
}