Vincenzo Rana, Ivan Beretta, Francesco Bruschi, Alessandro Antonio Nacci, David Atienza, Donatella Sciuto. Efficient Hardware Design of Iterative Stencil Loops. IEEE Trans. on CAD of Integrated Circuits and Systems, 35(12):2018-2031, 2016. [doi]
@article{RanaBBNAS16,
title = {Efficient Hardware Design of Iterative Stencil Loops},
author = {Vincenzo Rana and Ivan Beretta and Francesco Bruschi and Alessandro Antonio Nacci and David Atienza and Donatella Sciuto},
year = {2016},
doi = {10.1109/TCAD.2016.2545408},
url = {http://dx.doi.org/10.1109/TCAD.2016.2545408},
researchr = {https://researchr.org/publication/RanaBBNAS16},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {35},
number = {12},
pages = {2018-2031},
}