Ashay Rane, James Browne. Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics. In Pen-Chung Yew, Sangyeun Cho, Luiz DeRose, David J. Lilja, editors, International Conference on Parallel Architectures and Compilation Techniques, PACT '12, Minneapolis, MN, USA - September 19 - 23, 2012. pages 147-156, ACM, 2012. [doi]
@inproceedings{RaneB12, title = {Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics}, author = {Ashay Rane and James Browne}, year = {2012}, doi = {10.1145/2370816.2370838}, url = {http://doi.acm.org/10.1145/2370816.2370838}, researchr = {https://researchr.org/publication/RaneB12}, cites = {0}, citedby = {0}, pages = {147-156}, booktitle = {International Conference on Parallel Architectures and Compilation Techniques, PACT '12, Minneapolis, MN, USA - September 19 - 23, 2012}, editor = {Pen-Chung Yew and Sangyeun Cho and Luiz DeRose and David J. Lilja}, publisher = {ACM}, isbn = {978-1-4503-1182-3}, }