Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics

Ashay Rane, James Browne. Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics. In Pen-Chung Yew, Sangyeun Cho, Luiz DeRose, David J. Lilja, editors, International Conference on Parallel Architectures and Compilation Techniques, PACT '12, Minneapolis, MN, USA - September 19 - 23, 2012. pages 147-156, ACM, 2012. [doi]

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