Nagendran Rangan, Karam S. Chatha. A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. In 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India. pages 564-569, IEEE Computer Society, 2005. [doi]
@inproceedings{RanganC05,
title = {A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling},
author = {Nagendran Rangan and Karam S. Chatha},
year = {2005},
url = {http://csdl.computer.org/comp/proceedings/vlsid/2005/2264/00/22640564abs.htm},
tags = {optimization},
researchr = {https://researchr.org/publication/RanganC05},
cites = {0},
citedby = {0},
pages = {564-569},
booktitle = {18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2264-5},
}