A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling - researchr publication

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Nagendran Rangan, Karam S. Chatha. A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. In 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India. pages 564-569, IEEE Computer Society, 2005. [doi]

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