Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor

Jinli Rao, Tianyong Ao, Shu Xu, Kui Dai, Xuecheng Zou. Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor. IEICE Transactions, 101-D(11):2698-2705, 2018. [doi]

@article{RaoAXDZ18,
  title = {Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor},
  author = {Jinli Rao and Tianyong Ao and Shu Xu and Kui Dai and Xuecheng Zou},
  year = {2018},
  url = {http://search.ieice.org/bin/summary.php?id=e101-d_11_2698},
  researchr = {https://researchr.org/publication/RaoAXDZ18},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {101-D},
  number = {11},
  pages = {2698-2705},
}