High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs

Muzaffar Rao, Thomas Newe, Ian Grout, Avijit Mathur. High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs. Journal of Circuits, Systems, and Computers, 25(7), 2016. [doi]

Abstract

Abstract is missing.