Girish B. Ratanpal, Ronald D. Williams, Travis N. Blalock. An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks. IEEE Trans. Dependable Sec. Comput., 1(3):179-189, 2004. [doi]
@article{RatanpalWB04,
title = {An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks},
author = {Girish B. Ratanpal and Ronald D. Williams and Travis N. Blalock},
year = {2004},
url = {http://csdl.computer.org/comp/trans/tq/2004/03/q0179abs.htm},
tags = {analysis},
researchr = {https://researchr.org/publication/RatanpalWB04},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Dependable Sec. Comput.},
volume = {1},
number = {3},
pages = {179-189},
}