TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST - researchr publication authors

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Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. In 17th IEEE VLSI Test Symposium (VTS 99), 25-30 April 1999, San Diego, CA, USA. pages 398-406, IEEE Computer Society, 1999. [doi]

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