A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz

Vishnu Ravinuthula, William Bright, Mark Weaver, Kenneth Maclean, Scott Kaylor, Sidharth Balasubramanian, Jesse Coulon, Robert Keller, Bao Nguyen, Ebenezer Dwobeng. A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz. In 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016. pages 1-2, IEEE, 2016. [doi]

@inproceedings{RavinuthulaBWMK16,
  title = {A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz},
  author = {Vishnu Ravinuthula and William Bright and Mark Weaver and Kenneth Maclean and Scott Kaylor and Sidharth Balasubramanian and Jesse Coulon and Robert Keller and Bao Nguyen and Ebenezer Dwobeng},
  year = {2016},
  doi = {10.1109/VLSIC.2016.7573538},
  url = {http://dx.doi.org/10.1109/VLSIC.2016.7573538},
  researchr = {https://researchr.org/publication/RavinuthulaBWMK16},
  cites = {0},
  citedby = {0},
  pages = {1-2},
  booktitle = {2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016},
  publisher = {IEEE},
  isbn = {978-1-5090-0635-9},
}