Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL - researchr publication authors

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Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes. Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL. In David Al-Dabass, Alessandra Orsoni, Richard Cant, Ajith Abraham, editors, Proceedings of the 12th UKSim, International Conference on Computer Modelling and Simulation, Cambridge, UK, 24-26 March 2010. pages 153-158, IEEE, 2010. [doi]

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