Process variation tolerant 9T SRAM bitcell design

G. K. Reddy, Kapil Jainwal, Jawar Singh, Saraju P. Mohanty. Process variation tolerant 9T SRAM bitcell design. In Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni, editors, Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012. pages 493-497, IEEE, 2012. [doi]

Abstract

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