B. N. Manjunatha Reddy, H. N. Sheshagiri, B. R. Vijayakumar, Shanthala S. Implementation of Low Power 8-Bit Multiplier Using Gate Diffusion Input Logic. In Xingang Liu, Didier El Baz, Ching-Hsien Hsu, Kai Kang, Weifeng Chen, editors, 17th IEEE International Conference on Computational Science and Engineering, CSE 2014, Chengdu, China, December 19-21, 2014. pages 1868-1871, IEEE, 2014. [doi]
@inproceedings{ReddySVS14-0,
title = {Implementation of Low Power 8-Bit Multiplier Using Gate Diffusion Input Logic},
author = {B. N. Manjunatha Reddy and H. N. Sheshagiri and B. R. Vijayakumar and Shanthala S},
year = {2014},
doi = {10.1109/CSE.2014.342},
url = {http://dx.doi.org/10.1109/CSE.2014.342},
researchr = {https://researchr.org/publication/ReddySVS14-0},
cites = {0},
citedby = {0},
pages = {1868-1871},
booktitle = {17th IEEE International Conference on Computational Science and Engineering, CSE 2014, Chengdu, China, December 19-21, 2014},
editor = {Xingang Liu and Didier El Baz and Ching-Hsien Hsu and Kai Kang and Weifeng Chen},
publisher = {IEEE},
isbn = {978-1-4799-7981-3},
}