Hardware design of FFT polynomial multipliers

C. P. Renteria-Mejia, Alexander López-Parrado, Jaime Velasco-Medina. Hardware design of FFT polynomial multipliers. In IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, Chile, February 25-28, 2014. pages 1-4, IEEE, 2014. [doi]

@inproceedings{Renteria-MejiaL14,
  title = {Hardware design of FFT polynomial multipliers},
  author = {C. P. Renteria-Mejia and Alexander López-Parrado and Jaime Velasco-Medina},
  year = {2014},
  doi = {10.1109/LASCAS.2014.6820315},
  url = {http://dx.doi.org/10.1109/LASCAS.2014.6820315},
  researchr = {https://researchr.org/publication/Renteria-MejiaL14},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, Chile, February 25-28, 2014},
  publisher = {IEEE},
}