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Hardware design of FFT polynomial multipliers

C. P. Renteria-Mejia, Alexander López-Parrado, Jaime Velasco-Medina. Hardware design of FFT polynomial multipliers. In IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, Chile, February 25-28, 2014. pages 1-4, IEEE, 2014. [doi]

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