Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz. A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. J. Solid-State Circuits, 45(12):2850-2860, 2010. [doi]
@article{ReutemannRKBDTS10,
title = {A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS},
author = {Robert Reutemann and Michael Ruegg and Fran Keyser and John Bergkvist and Daniel Dreps and Thomas Toifl and Martin L. Schmatz},
year = {2010},
doi = {10.1109/JSSC.2010.2077350},
url = {http://dx.doi.org/10.1109/JSSC.2010.2077350},
researchr = {https://researchr.org/publication/ReutemannRKBDTS10},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {45},
number = {12},
pages = {2850-2860},
}