FPGA-Based Digital Signal Processing Trainer

Rosula S. Reyes, Carlos M. Oppus, Jose Claro N. Monje, Noel S. Patron, Raphael A. Gonzales, Jovilyn Therese B. Fajardo. FPGA-Based Digital Signal Processing Trainer. In Mark Burgin, Masud H. Chowdhury, Chan H. Ham, Simone A. Ludwig, Weilian Su, Sumanth Yenduri, editors, CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31 - April 2, 2009, Los Angeles, California, USA, 7 Volumes. pages 343-347, IEEE Computer Society, 2009. [doi]

Authors

Rosula S. Reyes

This author has not been identified. Look up 'Rosula S. Reyes' in Google

Carlos M. Oppus

This author has not been identified. Look up 'Carlos M. Oppus' in Google

Jose Claro N. Monje

This author has not been identified. Look up 'Jose Claro N. Monje' in Google

Noel S. Patron

This author has not been identified. Look up 'Noel S. Patron' in Google

Raphael A. Gonzales

This author has not been identified. Look up 'Raphael A. Gonzales' in Google

Jovilyn Therese B. Fajardo

This author has not been identified. Look up 'Jovilyn Therese B. Fajardo' in Google