A hardware architecture for filtering irreducible testors

Vladimir Rodriguez, Jose F. Martinez, Jesús Ariel Carrasco-Ochoa, Manuel S. Lazo, René Cumplido, Claudia Feregrino Uribe. A hardware architecture for filtering irreducible testors. In 2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig14, Cancun, Mexico, December 8-10, 2014. pages 1-4, IEEE, 2014. [doi]

Abstract

Abstract is missing.