Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs

Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay. Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs. Integration, 45(3):307-315, 2012. [doi]

@article{RoyRM12,
  title = {Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs},
  author = {Sujoy Sinha Roy and Chester Rebeiro and Debdeep Mukhopadhyay},
  year = {2012},
  doi = {10.1016/j.vlsi.2011.11.007},
  url = {http://dx.doi.org/10.1016/j.vlsi.2011.11.007},
  researchr = {https://researchr.org/publication/RoyRM12},
  cites = {0},
  citedby = {0},
  journal = {Integration},
  volume = {45},
  number = {3},
  pages = {307-315},
}