Dario Russo, Stefano Ricci. FPGA-Based Clock Phase Alignment Circuit for Frame Jitter Reduction. In Sergio Saponara, Alessandro De Gloria, editors, Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2019, Pisa, Italy, 11-13 September 2019. Volume 627 of Lecture Notes in Electrical Engineering, pages 199-205, Springer, 2019. [doi]
@inproceedings{RussoR19-0,
title = {FPGA-Based Clock Phase Alignment Circuit for Frame Jitter Reduction},
author = {Dario Russo and Stefano Ricci},
year = {2019},
doi = {10.1007/978-3-030-37277-4_23},
url = {https://doi.org/10.1007/978-3-030-37277-4_23},
researchr = {https://researchr.org/publication/RussoR19-0},
cites = {0},
citedby = {0},
pages = {199-205},
booktitle = {Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2019, Pisa, Italy, 11-13 September 2019},
editor = {Sergio Saponara and Alessandro De Gloria},
volume = {627},
series = {Lecture Notes in Electrical Engineering},
publisher = {Springer},
isbn = {978-3-030-37277-4},
}