FPGA-Based Clock Phase Alignment Circuit for Frame Jitter Reduction

Dario Russo, Stefano Ricci. FPGA-Based Clock Phase Alignment Circuit for Frame Jitter Reduction. In Sergio Saponara, Alessandro De Gloria, editors, Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2019, Pisa, Italy, 11-13 September 2019. Volume 627 of Lecture Notes in Electrical Engineering, pages 199-205, Springer, 2019. [doi]

Abstract

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