Abstract is missing.
- Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip InterconnectionsMark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar. 3-20 [doi]
- Run-Time Power-Gating Techniques for Low-Power On-Chip NetworksHiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano. 21-43 [doi]
- Adaptive Voltage Control for Energy-Efficient NoC LinksPaul Ampadu, Bo Fu, David Wolpert, Qiaoyan Yu. 45-69 [doi]
- Asynchronous Communications for NoCsStanislavs Golubcovs, Alex Yakovlev. 71-109 [doi]
- Application-Specific Routing Algorithms for Low Power Network on Chip DesignMaurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania. 113-150 [doi]
- Adaptive Data Compression for Low-Power On-Chip NetworksYuho Jin, Ki Hwan Yum, Eun Jung Kim 0001. 151-174 [doi]
- Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case StudyRudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny. 175-195 [doi]
- Design and Analysis of NoCs for Low-Power 2D and 3D SoCsCiprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli. 199-222 [doi]
- CMOS Nanophotonics: Technology, System Implications, and a CMP Case StudyJung Ho Ahn, Raymond G. Beausoleil, Nathan L. Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar, Robert Schreiber, Dana Vantrease. 223-254 [doi]
- RF-Interconnect for Future Network-On-ChipSai-Wang Tam, Eran Socher, Mau-Chung Frank Chang, Jason Cong, Glenn D. Reinman. 255-280 [doi]