A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment - researchr publication references

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Debapriya Sahu. A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. In Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India. pages 360-365, IEEE Computer Society, 2002. [doi]

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