19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC - researchr publication authors

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Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura. 19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 336-337, IEEE, 2016. [doi]

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