Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura. 19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 336-337, IEEE, 2016. [doi]
@inproceedings{SaiKTOFI16,
title = {19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC},
author = {Akihide Sai and Satoshi Kondo and Tuan Thanh Ta and Hidenori Okuni and Masanori Furuta and Tetsuro Itakura},
year = {2016},
doi = {10.1109/ISSCC.2016.7418044},
url = {http://dx.doi.org/10.1109/ISSCC.2016.7418044},
researchr = {https://researchr.org/publication/SaiKTOFI16},
cites = {0},
citedby = {0},
pages = {336-337},
booktitle = {2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016},
publisher = {IEEE},
isbn = {978-1-4673-9467-3},
}