Formal modeling and verification for pre-charge half buffer gates and circuits

Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan. Formal modeling and verification for pre-charge half buffer gates and circuits. In IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017. pages 519-522, IEEE, 2017. [doi]

Abstract

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