Constructing Effective UVM Testbench for DRAM Memory Controllers

Khaled Salah, Hassan Mostafa. Constructing Effective UVM Testbench for DRAM Memory Controllers. In 2018 New Generation of CAS, NGCAS 2018, Valletta, Malta, November 20-23, 2018. pages 178-181, IEEE, 2018. [doi]

@inproceedings{SalahM18,
  title = {Constructing Effective UVM Testbench for DRAM Memory Controllers},
  author = {Khaled Salah and Hassan Mostafa},
  year = {2018},
  doi = {10.1109/NGCAS.2018.8572135},
  url = {https://doi.org/10.1109/NGCAS.2018.8572135},
  researchr = {https://researchr.org/publication/SalahM18},
  cites = {0},
  citedby = {0},
  pages = {178-181},
  booktitle = {2018 New Generation of CAS, NGCAS 2018, Valletta, Malta, November 20-23, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-7681-3},
}