Juan Salamanca, José Nelson Amaral, Guido Araujo. Using Hardware Transactional Memory to Enable Speculative Trace Optimization. In 2015 International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PAD Workshops, Florianópolis, Brazil, October 18-21, 2015. pages 1-6, IEEE, 2015. [doi]
@inproceedings{SalamancaAA15,
title = {Using Hardware Transactional Memory to Enable Speculative Trace Optimization},
author = {Juan Salamanca and José Nelson Amaral and Guido Araujo},
year = {2015},
doi = {10.1109/SBAC-PADW.2015.13},
url = {http://dx.doi.org/10.1109/SBAC-PADW.2015.13},
researchr = {https://researchr.org/publication/SalamancaAA15},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {2015 International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PAD Workshops, Florianópolis, Brazil, October 18-21, 2015},
publisher = {IEEE},
isbn = {978-1-4673-8621-0},
}