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Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories

Juan Salamanca, José Nelson Amaral, Guido Araujo. Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories. In 2016 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016, Chicago, IL, USA, May 23-27, 2016. pages 586-595, IEEE Computer Society, 2016. [doi]

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Juan Salamanca

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José Nelson Amaral

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Guido Araujo

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