Juan Salamanca, José Nelson Amaral, Guido Araujo. Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories. In 2016 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016, Chicago, IL, USA, May 23-27, 2016. pages 586-595, IEEE Computer Society, 2016. [doi]
@inproceedings{SalamancaAA16,
title = {Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories},
author = {Juan Salamanca and José Nelson Amaral and Guido Araujo},
year = {2016},
doi = {10.1109/IPDPS.2016.84},
url = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2016.84},
researchr = {https://researchr.org/publication/SalamancaAA16},
cites = {0},
citedby = {0},
pages = {586-595},
booktitle = {2016 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016, Chicago, IL, USA, May 23-27, 2016},
publisher = {IEEE Computer Society},
isbn = {978-1-5090-2140-6},
}