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Juan Salamanca 0001, José Nelson Amaral, Guido Araujo. Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation. IEEE Trans. Parallel Distrib. Syst., 29(2):466-480, 2018. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional MemoriesJuan Salamanca, José Nelson Amaral, Guido Araujo. europar 2017: 607-621 [doi] Evaluating and Improving Thread-Level Speculation in Hardware Transactional MemoriesJuan Salamanca, José Nelson Amaral, Guido Araujo. ipps 2016: 586-595 [doi]
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