Valery Salauyou, Lukasz Zabrocki. Coding Techniques in Verilog for Finite State Machine Designs in FPGA. In Khalid Saeed 0001, Rituparna Chaki, Valentina Janev, editors, Computer Information Systems and Industrial Management - 18th International Conference, CISIM 2019, Belgrade, Serbia, September 19-21, 2019, Proceedings. Volume 11703 of Lecture Notes in Computer Science, pages 493-505, Springer, 2019. [doi]
@inproceedings{SalauyouZ19,
title = {Coding Techniques in Verilog for Finite State Machine Designs in FPGA},
author = {Valery Salauyou and Lukasz Zabrocki},
year = {2019},
doi = {10.1007/978-3-030-28957-7_41},
url = {https://doi.org/10.1007/978-3-030-28957-7_41},
researchr = {https://researchr.org/publication/SalauyouZ19},
cites = {0},
citedby = {0},
pages = {493-505},
booktitle = {Computer Information Systems and Industrial Management - 18th International Conference, CISIM 2019, Belgrade, Serbia, September 19-21, 2019, Proceedings},
editor = {Khalid Saeed 0001 and Rituparna Chaki and Valentina Janev},
volume = {11703},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-030-28957-7},
}