A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach

Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi. A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. In John Lach, Gang Qu, Yehea I. Ismail, editors, Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005. pages 296-301, ACM, 2005. [doi]

@inproceedings{SalehNNPS05,
  title = {A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach},
  author = {Kamran Saleh and Mehrdad Najibi and Mohsen Naderi and Hossein Pedram and Mehdi Sedighi},
  year = {2005},
  doi = {10.1145/1057661.1057733},
  url = {http://doi.acm.org/10.1145/1057661.1057733},
  tags = {systematic-approach},
  researchr = {https://researchr.org/publication/SalehNNPS05},
  cites = {0},
  citedby = {0},
  pages = {296-301},
  booktitle = {Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005},
  editor = {John Lach and Gang Qu and Yehea I. Ismail},
  publisher = {ACM},
  isbn = {1-59593-057-4},
}