A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri. A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. In 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India. pages 521-526, IEEE Computer Society, 2008. [doi]

Abstract

Abstract is missing.