Harsha Keerthan Samudrala, Shaik A. Qadeer, Syed Azeemuddin, Mohammed Zafar Ali Khan. Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm. In IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018. pages 21-26, IEEE, 2018. [doi]
@inproceedings{SamudralaQAK18,
title = {Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm},
author = {Harsha Keerthan Samudrala and Shaik A. Qadeer and Syed Azeemuddin and Mohammed Zafar Ali Khan},
year = {2018},
doi = {10.1109/iSES.2018.00015},
url = {https://doi.org/10.1109/iSES.2018.00015},
researchr = {https://researchr.org/publication/SamudralaQAK18},
cites = {0},
citedby = {0},
pages = {21-26},
booktitle = {IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018},
publisher = {IEEE},
isbn = {978-1-5386-9172-4},
}