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Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm

Harsha Keerthan Samudrala, Shaik A. Qadeer, Syed Azeemuddin, Mohammed Zafar Ali Khan. Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm. In IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018. pages 21-26, IEEE, 2018. [doi]

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