Parametrized Verification Diagrams

Alejandro Sánchez, César Sánchez. Parametrized Verification Diagrams. In Amedeo Cesta, Carlo Combi, François Laroussinie, editors, 21st International Symposium on Temporal Representation and Reasoning, TIME 2014, Verona, Italy, September 8-10, 2014. pages 132-141, IEEE, 2014. [doi]

Abstract

Abstract is missing.