A Self-Timed Pipeline Circuit for Low-Power Surrounding LSI Chips

Shuji Sannomiya, Kazuhiro Komatsu, Makoto Iwata. A Self-Timed Pipeline Circuit for Low-Power Surrounding LSI Chips. In Hamid R. Arabnia, editor, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, Volume 2. pages 613-622, CSREA Press, 2007.

Abstract

Abstract is missing.